Memory device and memory system

ABSTRACT

A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation-in-part (CIP) of U.S. application Ser. No. 15/379,122, filed Dec. 14, 2016, the disclosure of which is incorporated herein by reference in its entirety. A claim for priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 10-2016-0022008, filed on Feb. 24, 2016, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The inventive concept herein relates to a memory device, and more particularly, to a memory device and a memory system including a memory controller for controlling generation of a programming voltage and a verifying voltage.

Semiconductor memory devices may be classified into volatile memory devices such as dynamic random-access memories (DRAMs) and static RAMs (SRAMs) for example, and nonvolatile memory devices such as electrically erasable programmable read-only memories (EEPROMs), ferroelectric RAMs (FRAMs), phase-change RAMs (PRAMs), magnetoresistive RAMs (MRAMs), and flash memories for example. Volatile memory devices lose stored data when power is turned off, whereas nonvolatile memory devices preserve stored data even when power is turned off.

The availability and widespread use of electronic devices including nonvolatile memory devices have rapidly increased. For example, MP3 players, digital cameras, mobile phones, camcorders, flash cards, and solid-state disks (SSDs) typically include nonvolatile memory devices as storage devices. As the use and capabilities of electronic devices including nonvolatile memory devices as storage devices have increased, the storage capacity of nonvolatile memory devices has consequently increased. The storage capacity of a memory device may be increased by employing a multi-level cell (MLC) method in which a plurality of bits are stored in one memory cell. In order to recognize data stored in an MLC, a sufficient read margin must be secured. A general programming method which secures sufficient read margin may include a programming operation based on an incremental step pulse programming (ISPP) scheme in which programming states of memory cells are verified using a plurality of verifying voltages whenever a programming voltage pulse is applied to the memory cells. However, even after such a verifying operation is completed, the reliability of data stored in the memory cells is reduced due to memory cell characteristics.

SUMMARY

Embodiments of the inventive concept provide a memory device and a memory system including memory cells with improved reliability of stored data.

Embodiments of the inventive concept provide a memory device including a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to each of the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.

Embodiments of the inventive concept further provide a memory device including a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply verifying voltages to the memory cell array, for verifying programming states of the memory cells; and a voltage controller configured to control the voltage generator so that levels of the verifying voltages gradually decrease as a program loop count increases.

Embodiments of the inventive concept also provide a memory system including a memory device including memory cells on which a programming loop is executed a plurality of times; and a memory controller configured to control the programming loop executed on the memory device. The memory device includes a voltage controller configured to control generation of verifying voltages having levels that are changed as a program loop count increases based on at least one of temperature information about a temperature inside or outside the memory device and programming states of the memory cells to be verified.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a block diagram of a memory system according to an embodiment of the inventive concept;

FIG. 2 illustrates a detailed block diagram of a memory device included in the memory system of FIG. 1 ;

FIG. 3 illustrates a circuit diagram of an equivalent circuit of a first block of FIG. 2 ;

FIG. 4 illustrates a perspective view of the first block of FIG. 2 according to an embodiment of the inventive concept;

FIG. 5 illustrates a graph of a programming voltage applied to a memory cell during a programming operation according to an embodiment of the inventive concept;

FIG. 6 illustrates a graph of a threshold voltage distribution of memory cells after a programming operation is completed;

FIGS. 7A, 7B and 7C each illustrate a distribution graph of a program loop count needed until each programming state is formed when a pulse-type programming voltage is applied to memory cells;

FIGS. 8A and 8B illustrate graphs showing a change in a threshold voltage of a memory cell according to memory cell characteristics and temperature;

FIGS. 9A and 9B illustrate graphs showing a threshold voltage distribution according to characteristics of a memory cell of FIG. 8 ;

FIG. 10 illustrates a block diagram of a voltage controller according to an embodiment of the inventive concept;

FIGS. 11A and 11B illustrate diagrams of control information needed during an operation of the voltage controller according to an embodiments of the inventive concept;

FIGS. 12A, 12 b and 12C illustrate graphs for explaining an operation of the voltage controller to control changing of a level of a verifying voltage according to an embodiments of the inventive concept;

FIGS. 13A, 13B, 13C and 13D illustrate graphs for explaining an operation of the voltage controller to control changing of a level of a verifying voltage according to various embodiments of the inventive concept;

FIGS. 14A and 14B each illustrate a block diagram for explaining a control operation of a voltage controller according to embodiments of the inventive concept;

FIG. 15 illustrates a block diagram for explaining an operation of a program loop counter according to an embodiment of the inventive concept;

FIG. 16 illustrates a block diagram of a voltage controller according to another embodiment of the inventive concept;

FIGS. 17A and 17B each illustrate a graph for explaining an operation of the voltage controller to control changing of a level of a verifying voltage according to the embodiment of FIG. 16 ;

FIG. 18A illustrates a block diagram for explaining an operation of a voltage controller to control changing of a level of a verifying voltage according to another embodiment of the inventive concept;

FIG. 18B illustrates a diagram of control information needed during an operation of the voltage controller according to another embodiment of the inventive concept;

FIG. 19A illustrates a block diagram for explaining an operation of a voltage controller to control changing of a level of a verifying voltage according to another embodiment of the inventive concept;

FIG. 19B illustrates a graph for explaining a method of a temperature information generator to generate temperature information according to the embodiment described with respect to FIG. 19A;

FIGS. 20A and 20B illustrate graphs for explaining an overall operation of a voltage controller according to an embodiment of the inventive concept;

FIG. 21 illustrates a flowchart for explaining a programming operation performed in a memory device according to an embodiment of the inventive concept;

FIG. 22 illustrates a block diagram of an example of applying a memory device to a memory card system according to embodiments of the inventive concept;

FIG. 23 illustrates a block diagram of a computing system including a memory device according to embodiments of the inventive concept;

FIG. 24 illustrates a block diagram of an example of applying a memory device to a solid-state disk (SSD) system according to embodiments of the inventive concept;

FIG. 25 illustrates a block diagram of an example of applying a memory device to a universal flash storage (UFS) system according to embodiments of the inventive concept;

FIG. 26 is a diagram illustrating a memory device according to another example embodiment;

FIG. 27 is a circuit diagram illustrating first and second mats included in a cell region of FIG. 26 ;

FIG. 28 is a block diagram of a memory device according to an example embodiment of the inventive concept; and

FIG. 29 is a view for describing a cell region of FIG. 26

DETAILED DESCRIPTION

The inventive concept will now be described more fully with reference to the accompanying drawings, in which various embodiments are shown.

As is traditional in the field of the inventive concept, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the inventive concept. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the inventive concept.

FIG. 1 illustrates a block diagram of a memory system 10 according to an embodiment of the inventive concept.

Referring to FIG. 1 , the memory system 10 includes a memory device 100 and a memory controller 200. The memory device 100 includes a memory cell array 110 and a control logic 120.

The memory cell array 110 may include a plurality of memory cells. The plurality of memory cells may be, for example, flash memory cells. It is assumed in the following description that the plurality of memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto, and in other embodiments, the plurality of memory cells may for example be resistive memory cells such as resistive random-access memories (RRAMs), phase-change RAMs (PRAMs), or magnetic RAMs (MRAMs).

In an embodiment, the memory cell array 110 may be a three-dimensional (3D) memory array. The 3D memory array may be monolithically formed at one or more physical levels of memory cell arrays having an active area disposed over a silicon substrate and circuitry associated with operations of memory cells and formed over or in the silicon substrate. The term “monolithic” means that layers of each level of the array are directly stacked on layers of each underlying level of the array.

In an embodiment, the 3D memory array includes NAND strings that are vertically oriented so that at least one memory cell is located over another memory cell. The at least one memory cell may include a charge trap layer. Suitable configurations for 3D memory arrays in which 3D memory arrays are configured as a plurality of levels and word lines and/or bit lines are shared between the levels are disclosed in U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Publication No. 2011-0233648, which are hereby incorporated by reference. Also, U.S. Patent Publication No. 2014-0334232 and U.S. Pat. No. 8,488,381 are hereby incorporated by reference.

In the present embodiment, the memory cell array 110 may include a plurality of NAND strings, and each of the NAND strings may include a ground selection transistor connected to a ground selection line, memory cells connected to word lines, and a string selection transistor connected to a string selection line, which are vertically stacked on a substrate. The NAND string may include more than one ground selection transistor, and/or more than one string selection transistor. In the present embodiment, the control logic 120 may control changing of a level of a verifying voltage when a programming loop including a programming operation and a verifying operation is executed on memory cells selected from among the memory cells included in the memory cell array 110. In an embodiment, the control logic 120 may gradually change levels of a plurality of verifying voltages based on at least one of a programming state of the memory cells to be verified and temperature information about a temperature inside or outside the memory device 100.

The memory controller 200 may control the memory device 100 to read data stored in the memory device 100 or write data to the memory device 100 in response to a read/write request from a host HOST. In detail, the memory controller 200 may control a programming (or write) operation, a read operation, and an erase operation to be performed on the memory device 100 by applying an address ADDR, a command CMD, and a control signal CTRL to the memory device 100. Also, data DATA for a programming operation and read data DATA may be transmitted/received between the memory controller 200 and the memory device 100.

Although not shown in FIG. 1 , the memory controller 200 may include a RAM, a processing unit, a host interface, and a memory interface. The RAM may be used as a working memory of the processing unit, and the processing unit may control an operation of the memory controller 200. The host interface may include a protocol for performing data exchange between the host HOST and the memory controller 200. For example, the memory controller 200 may be configured to communicate with the host HOST through at least one of various interface protocols such as a universal serial bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-E), advanced technology attachment (ATA), serial-ATA, parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (ESDI), and integrated drive electronics (IDE).

FIG. 2 illustrates a detailed block diagram of the memory device 100 included in the memory system 10 of FIG. 1 .

Referring to FIG. 2 , the memory device 100 includes the memory cell array 110, a read-only memory (ROM) fuse 112, the control logic 120, a voltage generator 130, a row decoder 140, and a page buffer 150. Although not shown in FIG. 2 , the memory device 100 may further include a data input/output circuit or an input/output interface.

The memory cell array 110 may include a plurality of memory cells, and may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. In detail, the memory cell array 110 may be connected to the row decoder 140 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL, and may be connected to the page buffer 150 through the bit lines BL.

The memory cell array 110 may include a plurality of blocks, e.g., first through z^(th) blocks BLK1, BLK2 through BLKz, and each block may have a 3D structure (or a vertical structure). In detail, each block includes structures that extend in first through third directions. For example, each block includes a plurality of NAND strings (hereinafter, referred to as ‘strings’) that extend in the third direction. In this case, the plurality of strings may be spaced apart from one another in the first and second directions. One of the first through z^(th) blocks BLK1 through BLKz may be selected by the row decoder 140. For example, the row decoder 140 may select a block corresponding to a block address from among the first through z^(th) blocks BLK1 through BLKz.

The memory cell array 110 may include at least one of a single-level cell block including single-level cells, a multi-level cell block including multi-level cells, and a triple-level cell block including triple-level cells. In other words, some blocks from among the plurality of blocks included in the memory cell array 110 may be single-level cell blocks and other blocks may be multi-level cell blocks or triple-level cell blocks.

The ROM fuse 112 may include memory cells having the same structure as that of the memory cells of the memory cell array 110. Although the ROM fuse 112 is located adjacent to the memory cell array 110 in FIG. 2 , the inventive concept is not limited thereto, and the ROM fuse 112 may be located far away from the memory cell array 110 or may be a part of the memory cell array 110. Pieces of information needed to generate a verifying voltage and a programming voltage generated to execute a programming loop on the memory cells may be stored in the ROM fuse 112. In an embodiment, the ROM fuse 112 may store control information including control parameters needed to gradually change a level of a verifying voltage as a programming loop is executed. In an embodiment, pieces of parameter information may include at least one of a change start verify voltage level parameter, a level change degree parameter, and a level change start loop parameter. In another embodiment, the pieces of parameter information may include at least one of a verifying voltage parameter and a program loop number parameter. A detailed explanation of the pieces of parameter information will be explained below.

The control logic 120 may output various control signals for writing data to the memory cell array 110 or reading data from the memory cell array 110 based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller 200. Accordingly, the control logic 120 may control overall various operations in the memory device 100.

The various control signals output from the control logic 120 may be applied to the voltage generator 130, the row decoder 140, and the page buffer 150. In detail, the control logic 120 may include a voltage controller 121. The voltage controller 121 may apply a voltage control signal CTRL_vol to the voltage generator 130. In an embodiment, the voltage controller 121 may generate the voltage control signal CTRL_vol for controlling generation of a verifying voltage and a programming voltage applied to the memory cell array 110 in order to write data to the memory cells.

In an embodiment, the voltage controller 121 may generate the voltage control signal CTRL_vol so that voltage levels of verifying voltages gradually decrease as a program loop count for the memory cells increases. Also, the voltage controller 121 may generate the voltage control signal CTRL_vol by referring to information that is stored in the ROM fuse 112. In another embodiment, the voltage controller 121 may generate the voltage control signal CTRL_vol so that verifying voltages for verifying programming states have different level change start timings. Also, the voltage controller 121 may generate the voltage control signal CTRL_vol so that verifying voltages have different level change degrees based on a programming state of memory cells to be verified. In an embodiment, the voltage controller 121 may generate the voltage control signal CTRL_vol so that the verifying voltages reach a level that is lower than reference voltage levels corresponding to verifying voltages. Also, the voltage controller 121 may generate the voltage control signal CTRL_vol so that a level of at least one verifying voltage from among verifying voltages is fixed after a programming loop is executed on the memory cells a predetermined number of times.

In another embodiment, the voltage controller 121 may generate the voltage control signal CTRL_vol so that levels of verifying voltages vary as a program loop count increases, based on temperature information about a temperature inside or outside the memory device 100. Also, the voltage controller 121 may generate the voltage control signal CTRL_vol to generate verifying voltages whereby at least one from among a level change degree and a change start verify voltage is changed, based on the temperature information. In another embodiment, the voltage controller 121 may generate the voltage control signal CTRL_vol in order to control generation of verifying voltages whose levels vary as a program loop count increases based on at least one of the temperature information and a programming state to be verified. Also, the voltage controller 121 may generate the voltage control signal CTRL_vol in order to control generation of verifying voltages whereby at least one from among a level change degree and a change start verify voltage is changed.

The voltage generator 130 may generate various voltages (indicated generally as VWL in FIG. 2 ) for performing programming, read, and erase operations on the memory cell array 110 based on the voltage control signal CTRL_vol. In detail, the voltage generator 130 may generate a word line voltage, for example, a programming voltage (or a write voltage), a read voltage, a programming inhibit voltage, a read inhibit voltage, or a verifying voltage. In an embodiment, the voltage generator 130 may generate a verifying voltage whose level varies as a program loop count increases based on the voltage control signal CTRL_vol. A programming loop may be executed by using an incremental step pulse programming (ISPP) scheme, and the voltage generator 130 may generate a programming voltage whose level increases by a step voltage from a previous programming voltage whenever a programming loop is executed.

The row decoder 140 may select some word lines from among the word lines WL in response to a row address X-ADDR received from the control logic 120. In detail, during a programming operation, the row decoder 140 may apply a programming voltage to the selected word lines and may apply a programming inhibit voltage to non-selected word lines. Also, the row decoder 140 may select some ground selection lines from among the ground selection lines GSL and some string selection lines from among the string selection lines SSL in response to the row address X-ADDR received from the control logic 120.

The page buffer 150 may be connected to the memory cell array 110 through the bit lines BL, and may select some bit lines from among the bit lines BL in response to a column address Y-ADDR received from the control logic 120. In detail, during a read operation, the page buffer 150 may operate as a sense amplifier and may detect data DATA stored in the memory cell array 110. During a programming operation, the page buffer 150 may operate as a write driver, and may input data DATA to be stored in the memory cell array 110.

FIG. 3 illustrates a circuit diagram of an equivalent circuit of the first block BLK1 of FIG. 2 .

Referring to FIG. 3 , the first block BLK1 may be a vertical NAND flash memory, and each of the first through z^(th) blocks BLK1 through BLKz of FIG. 2 may have the same form as that in FIG. 3 . The first block BLK1 may include a plurality of NAND strings NS11 through NS33, a plurality of word lines WL1 through WL8, a plurality of bit lines, e.g., first through third bit lines BL1 through BL3, a plurality of ground selection lines GSL1 through GSL3, a plurality of string selection lines SSL1 through SSL3, and a common source line CSL. The number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be changed in various ways.

The NAND strings NS11, NS21, and NS31 are provided between the first bit line BL1 and the common source line CSL, the NAND strings NS12, NS22, and NS32 are provided between the second bit line BL2 and the common source line CSL, and the NAND strings NS13, NS23, and NS33 are provided between the third bit line BL3 and the common source line CSL. Each NAND string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC1 through MC8, and a ground selection transistor GST that are serially connected. Hereinafter, a NAND string is referred to as a string for convenience of explanation.

Strings commonly connected to one bit line constitute one column. For example, the strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 may correspond to a first column, the strings NS12, NS22, and NS32 commonly connected to the second bit line BL2 may correspond to a second column, and the strings NS13, NS23, and NS33 commonly connected to the third bit line BL3 may correspond to a third column.

Strings connected to one string selection line constitute one row. For example, the strings NS11, NS12, and NS13 connected to the first string selection line SSL1 may correspond to a first row, the strings NS21, NS22, and NS23 connected to the second string selection line SSL2 may correspond to a second row, and the strings NS31, NS32, and NS33 connected to the third string selection line SSL3 may correspond to a third row.

The string selection transistors SST are respectively connected to the string selection lines SSL1 through SSL3. The plurality of memory cells MC1 through MC8 are respectively connected to the word lines WL1 through WL8. The ground selection transistors GST are respectively connected to the ground selection lines GSL1 through GSL3. The string selection transistors SST are also respectively connected to the first through third bit lines BL1 through BL3, and the ground selection transistors GST are connected to the common source line CSL.

In the present embodiment, the word lines having the same height (e.g., WL1) are connected to one another, the string selection lines SSL1 through SSL3 are separated from one another, and the ground selection lines GSL1 through GSL3 are separated from one another. For example, when memory cells connected to the first word line WL1 and included in the strings NS11, NS12, and NS13 are programmed, the first word line WL1 and the first string selection line SSL1 are selected. However, the inventive concept is not limited thereto, and in another embodiment, the ground selection lines GSL1 through GSL3 may be connected to one another.

FIG. 4 illustrates a perspective view of the first block BLK1 of FIG. 2 according to an embodiment of the inventive concept.

Referring to FIG. 4 , the first block BLK1 is formed in a direction perpendicular to a substrate SUB. Although the first block BLK1 includes two selection lines GSL and SSL, eight word lines WL1 through WL8, and three bit lines BL1 through BL3 in FIG. 4 , the first block BLK1 may actually include fewer or more lines.

The substrate SUB has a first conductivity type (e.g., a p-type), and the common source line CSL extends in a first direction (e.g., a Y direction) on the substrate SUB and is doped with impurities having a second conductivity type (e.g., an n-type). A plurality of insulating films IL that extend in the first direction are sequentially provided in a third direction (e.g., a Z direction) on a portion of the substrate SUB between two adjacent common source lines CSL, and are spaced apart by a predetermined distance from each other in the third direction. For example, the plurality of insulating films IL may include an insulating material such as silicon oxide.

A plurality of pillars P that pass through the plurality of insulating films IL in the third direction and are sequentially arranged in the first direction are provided on a portion of the substrate SUB between two adjacent common source lines CSL. For example, the plurality of pillars P may pass through the plurality of insulating films IL and may contact the substrate SUB. In detail, a surface layer S of each of the pillars P may include a silicon material having a first conductivity type and may function as a channel region. An inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

A charge storage layer CS is provided along exposed surfaces of the insulating films IL, the pillars P, and the substrate SUB in a portion between two adjacent common source lines CSL. The charge storage layer CS may include a gate insulating layer (or referred to as a ‘tunneling insulating layer’), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Also, a gate electrode GE such as each of the selection lines GSL and SSL and the word lines WL1 through WL8 is provided on an exposed surface of the charge storage layer CS in a portion between two adjacent common source lines CSL. A ground selection transistor GST is adjacent the substrate SUB.

Drains or drain contacts DR are provided on the plurality of pillars P. For example, the drains or drain contacts DR may include a silicon material doped with impurities having a second conductivity type. A string selection transistor SST is adjacent the drain contact DR. The first through third bit lines BL1 through BL3 that extend in a second direction (e.g., an X direction) and are spaced apart by a predetermined distance from each other in the first direction are provided on the drain or drain contacts DR.

According to the present embodiment, charges trapped in a predetermined region of the charge storage layer CS as a result of a programming operation may escape from the predetermined region and may be trapped in another region or may move to another layer other than the charge storage layer CS, thereby widening a threshold voltage distribution of memory cells. Accordingly, the reliability of a memory device including the charge storage layer CS may be reduced, which will be explained in detail below.

FIG. 5 illustrates a graph of a programming voltage applied to a memory cell during a programming operation according to an embodiment of the inventive concept. In FIG. 5 , the vertical axis represents a programming voltage Vpgm, and the horizontal axis represents a program loop number.

Referring to FIGS. 2 and 5 , the voltage generator 130 may apply a programming voltage Vpgm operation to a selected word line of the memory cell array 110. A level of the programming voltage Vpgm increases by a step voltage Vstep whenever a programming loop is executed during a programming. Also, the voltage generator 130 may apply a verifying voltage to the selected word line of the memory cell array 110 in order to perform a verifying operation for verifying a programming state after a programming voltage Vpgm is applied.

FIG. 6 illustrates a graph of a threshold voltage distribution of memory cells after a programming operation is completed. In FIG. 6 , the vertical axis represents a number of programmed memory cells, and the horizontal axis represents a threshold voltage.

Referring to FIG. 6 , each memory cell according to an embodiment may be a multi-bit cell, and thus two or more bits of data may be stored in one memory cell. A threshold voltage distribution of memory cells having four programming states may be formed as shown in FIG. 6 by performing a programming operation by using an ISPP scheme of FIG. 5 . Each memory cell may have an erase state E, a first programming state P1, a second programming state P2, or a third programming state P3 as a result of the programming operation. The voltage generator 130 of FIG. 2 may perform a verifying operation for verifying whether memory cells are in the first programming state P1 as a result of the programming operation by using a first verifying voltage VP1. Also, the voltage generator 130 may perform a verifying operation for verifying whether the memory cells are in the second programming state P2 by using a second verifying voltage VP2. The voltage generator 130 may perform a verifying operation for verifying whether the memory cells are in the third programming state P3 by using a third verifying voltage VP3. Although a memory device including memory cells in which two bits of data is stored is described, the inventive concept is not limited thereto. Thus, in an embodiment, a memory device including multi-level cells MLCs in which a plurality of bits of data may be stored and that may have a plurality of programming states may be used.

FIGS. 7A, 7B and 7C each illustrate a distribution graph of a program loop count needed until each programming state is reached when a pulse-type programming voltage is applied to memory cells. In FIGS. 7A-7C, the vertical axes represent a number of programmed memory cells, and the horizontal axes represent a program loop number.

Referring to FIG. 7A, a number of times a programming loop is repeatedly executed until a threshold voltage of a predetermined memory cell exceeds the first verifying voltage VP1 of FIG. 6 and the predetermined memory cell reaches the first programming state P1 may vary according to memory cells. That is, fast cells FC₁ may reach the first programming state P1 after a programming loop is executed thereon a relatively small number of times. Slow cells SC₁ may reach the first programming state P1 after a programming loop is executed thereon a relatively large number of times.

Referring to FIG. 7B, the number of times a programming loop is repeatedly executed until a threshold voltage of a predetermined memory cell exceeds the second verifying voltage VP2 of FIG. 6 and the predetermined memory cell reaches the second programming state P2 may vary according to memory cells. That is, fast cells FC₂ may reach the second programming state P2 after a programming loop a is executed thereon a relatively small number of times, and slow cells SC₂ may reach the second programming state P2 after a programming loop is executed thereon a relatively large number of times.

Referring to FIG. 7C, the number of times a programming loop is repeatedly executed until a threshold voltage of a predetermined memory cell exceeds the third verifying voltage VP3 of FIG. 6 and the predetermined memory cell reaches the third programming state P3 may vary according to memory cells. That is, fast cells FC₃ may reach the third programming state P3 by executing a programming loop a relatively small number of times, and slow cells SC₃ may reach the third programming state P3 by executing a programming loop a relatively large number of times.

As such, there may exist memory cells whose threshold voltages are rapidly changed and memory cells whose threshold voltages are slowly changed when a programming loop is executed.

FIGS. 8A and 8B illustrate graphs showing a change in a threshold voltage of a memory cell according to memory cell characteristics and a temperature. In FIGS. 8A and 8B, the vertical axes of the graphs represent threshold voltage, and the horizontal axes represent time.

FIG. 8A illustrates graphs showing a relationship between a threshold voltage of memory cells and a time under a first temperature condition. A graph (a) in FIG. 8A illustrates a change in a threshold voltage of memory cells having the first programming state P1. A graph (b) in FIG. 8A illustrates a change in a threshold voltage of memory cells having the second programming state P2. Also, a graph (c) in FIG. 8A illustrates a change in a threshold voltage of memory cells having the third programming state P3. Referring to FIG. 8A, a change amount of a threshold voltage per time increases as a programming state has a greater threshold voltage, and a change amount of a threshold voltage of a fast cell per time is greater than a change amount of a threshold voltage of a slow cell per time.

FIG. 8B illustrates graphs showing a relationship between a threshold voltage of memory cells and a time under a second temperature condition. The second temperature condition may have a temperature lower than a temperature of the first temperature condition. For example, the first temperature condition may correspond to a temperature of 80° C. and the second temperature condition may correspond to a temperature of −10° C. Referring to FIG. 8B, a change amount of a threshold voltage per time increases as a programming state has a greater threshold voltage, and a change amount of a threshold voltage of a fast cell per time is greater than a change amount of a threshold voltage of a slow cell per time. Furthermore, a difference between a change amount of a threshold voltage of a fast cell per time and a change amount of a threshold voltage of a slow cell per time increases as a temperature of a temperature condition decreases.

FIGS. 9A and 9B illustrate graphs showing a threshold voltage distribution according to memory cell characteristics of FIGS. 8A and 8B. In FIGS. 9A and 9B, the vertical axes represent a number of programmed memory cells, and the horizontal axes represent a threshold voltage.

As shown in FIG. 9A, since a threshold voltage of memory cells varies as time passes, a threshold voltage distribution of memory cells after a programming operation is completed may be changed. For example, a threshold voltage of some memory cells having the first programming state P1 may be shifted leftward by a first interval a1, a threshold voltage of some memory cells having the second programming state P2 may be shifted leftward by a second interval a2, and a threshold voltage of some memory cells having the third programming state P3 may be shifted leftward by a third interval a3. In this case, a change amount of a threshold voltage distribution may increase as memory cells have a programming state requiring a higher verifying voltage level in order to perform a verifying operation, that is, have a higher threshold voltage, and thus the third interval a3 may be greater than the second interval a2 and the second interval a2 may be greater than the first interval a1.

As shown in FIG. 9B, since a difference between a change amount of a threshold voltage of a fast cell per time and a change amount of a threshold voltage of a slow cell per time increases as a temperature condition decreases, a change amount of a threshold voltage distribution of memory cells under a temperature condition having a temperature lower than that in FIG. 9A may be greater than that in FIG. 9A. That is, a threshold voltage of some memory cells having the first programming state P1 may be shifted leftward by a first interval b1, a threshold voltage of some memory cells having the second programming state P2 may be shifted leftward by a second interval b2, and a threshold voltage of some memory cells having the third programming state P3 may be shifted leftward by a third interval b3. The first through third intervals b1 through b3 of FIG. 9B may be respectively greater than the first through third intervals a1 through a3 of FIG. 9A.

FIG. 10 illustrates a block diagram of a voltage controller 200 according to an embodiment of the inventive concept. FIGS. 11A and 11B illustrate diagrams of control information needed during an operation of the voltage controller 200 according to embodiments of the inventive concept. FIGS. 12A through 12C illustrate graphs for explaining an operation of the voltage controller 200 to control changing of a level of a verifying voltage according to an embodiments of the inventive concept. The voltage controller 200 may correspond to the voltage controller 121 of control logic 120 shown in FIG. 2 . Also, in FIGS. 12A-12C the vertical axes represent a verify voltage, and the horizontal axes represent a program loop.

Referring to FIG. 10 , the voltage controller 200 includes a program loop counter 210, a verifying voltage level control signal generator 220, and a control information storage unit 230. The program loop counter 210 counts the number of times a programming loop is executed on memory cells. In an embodiment, the program loop counter 210 may count the number of repetitions of a programming loop by counting a number of pulses when a programming voltage is stepped up. The program loop counter 210 may generate program loop count information by counting the number of repetitions of a programming loop and may send the program loop count information to the verifying voltage level control signal generator 220. Also, in an embodiment (which will be described later with respect to FIG. 14A for example), the program loop counter 210 may control the verifying voltage level control signal generator 220 to be activated/deactivated based on the program loop count information provided from the control information storage unit 230.

The verifying voltage level control signal generator 220 generates a voltage control signal CTRL_vol1 for controlling a verifying voltage generated by a voltage generator, the verifying voltage to be generated having a level that varies as a program loop count increases. The verifying voltage level control signal generator 220 may receive control information for controlling changing of a verifying voltage from the control information storage unit 230, and may receive the program loop count information from the program loop counter 210. The verifying voltage level control signal generator 220 may control changing of a level of a verifying voltage by using the program loop count information and the control information.

The control information storage unit 230 may store pieces of control information needed to change a level of a verifying voltage. The pieces of control information may include a change start verify voltage level parameter, a level change degree parameter, and a level change start loop parameter, and may further include a program loop number parameter and a verifying voltage level parameter corresponding to the program loop number parameter. The pieces of control information may be stored in the ROM fuse 112 when the memory device 100 of FIG. 2 is turned off and may be loaded to the control information storage unit 230 when the memory device 100 is turned on. The control information storage unit 230 may apply the pieces of control information to the verifying voltage level control signal generator 220. However, the inventive concept is not limited thereto, and the verifying voltage level control signal generator 220 may directly receive the pieces of control information from the ROM fuse 112.

Referring to FIG. 11A, the control information stored in control information storage unit 230 may include control parameters including a change start verify voltage level parameter SVL, a level change degree parameter LCD, and a level change start loop parameter SL according to each programming state to be verified (e.g., P1, P2 and P3). The change start verify voltage level parameter SVL is a parameter that is referred to in order to control a start level of a verifying voltage when the voltage controller 200 starts to control changing of a level of the verifying voltage. The level change degree parameter LCD is a parameter that is referred to in order to control, when the voltage controller 200 controls changing of a level of the verifying voltage, a level change degree of the verifying voltage. The level change start loop parameter SL is a parameter that is referred to in order for the voltage controller 200 to control a level change start timing of a verifying voltage. The verifying voltage level control signal generator 220 may generate the voltage control signal CTRL_vol1 for controlling the voltage generator by using the above control information.

Referring to FIG. 11B, the control information stored in control information storage unit 230 may further include control parameters including a verifying voltage level parameter VVL and a program loop number parameter PLN according to each programming state to be verified (e.g., P1, P2 and P3). The program loop number parameter PLN and the verifying voltage level parameter VVL may be parameters that are referred to in order for the voltage controller 200 to generate a verifying voltage having a predetermined level when a predetermined programming loop is executed. The verifying voltage level control signal generator 220 may generate the voltage control signal CTRL_vol1 for controlling the voltage generator by using the above control information.

An operation of the voltage controller 200 to control changing of a level of the first verifying voltage VP1 for verifying the first programming state P1 of FIG. 6 will now be explained with reference to FIGS. 10, 11A, and 12A. In an embodiment, the voltage controller 200 may control generation of a first verifying voltage (by voltage generator 130 of FIG. 2 ) whose level gradually decreases as a programming loop is executed on memory cells. That is, a verifying voltage whose level decreases as a programming loop is executed as L, L+1, . . . may be generated as shown in FIG. 12A. Also, the voltage controller 200 may control generation of a verifying voltage whose level gradually decreases by a predetermined level change degree from a level of a change start verify voltage. In an embodiment, the voltage controller 200 may set the change start verify voltage to a 1-1 verifying voltage V_(va1) for programming loop L by using the change start verify voltage level parameter SVL, and may set a level change degree to a first offset voltage V_(os1) by using the level change degree parameter LCD. The voltage controller 200 may control generation of a first verifying voltage whose level decreases by the first offset voltage V_(os1) from the 1-1 verifying voltage V_(va1) as a programming loop is executed.

As shown in FIG. 12A as an example, the 1-1 verifying voltage V_(va1) for programming loop L is decreased by the first offset voltage V_(os1) to 1-2 verifying voltage V_(va2) for programming loop L+1. That is, for example, the 1-2 verifying voltage V_(va2) having a second level which is less than a first level (the 1-1 verifying voltage V_(va1)) is applied to memory cells that fail to pass the verifying operation using the first level verifying voltage. As further shown, the 1-2 verifying voltage V_(va2) for programming loop L+1 is decreased by the first offset voltage V_(os1) to 1-3 verifying voltage V_(va3) for programming loop L+2. The 1-3 verifying voltage V_(va3) for programming loop L+2 is decreased by the first offset voltage V_(os1) to 1-4 verifying voltage V_(va4) for programming loop L+3. The 1-4 verifying voltage V_(va4) for programming loop L+3 is decreased by the first offset voltage V_(os1) to 1-5 verifying voltage V_(va5) for programming loop L+4. The 1-5 verifying voltage V_(va5) for programming loop L+4 is decreased by the first offset voltage V_(os1) to 1-6 verifying voltage V_(va6) for programming loop L+5. Incidentally, in this description a 1-1 verifying voltage should be understood whereby the notation “1-1” is indicative of a first verifying voltage (e.g., VP1 in FIG. 6 ) during a first programming loop. Likewise, a 1-2 verifying voltage may be indicative of a first verifying voltage (e.g., VP1) during a second programming loop, and a 2-1 verifying voltage may be indicative of a second verifying voltage (e.g., VP2 in FIG. 6 ) during a first programming loop.

In an embodiment, the change start verify voltage may have a level higher than a level of a verifying voltage for verifying a programming state. For example, a level of the 1-1 verifying voltage V_(va1) may be higher than a level of a verifying voltage conventionally generated to verify a first programming state.

In this manner, a level of a verifying voltage may be changed in consideration that a threshold voltage of memory cells gradually decreases as a time passes and a change amount of a threshold voltage of a fast cell is greater than a change amount of a threshold voltage of a slow cell. Accordingly, memory cells of a memory device according to the inventive concept may have a constant threshold voltage distribution even when a predetermined period of time passes, thereby improving the reliability of the memory device.

In another embodiment, the voltage controller 200 may control a level of a verifying voltage to be changed in programming loops after a level change start loop. For example, the voltage controller 200 may set an L^(th) programming loop to a level change start loop by using the level change start loop parameter SL. The voltage controller 200 may control a level of a first verifying voltage to be changed in programming loops L+1, L+2, . . . after the L^(th) programming loop. In this manner, the voltage controller 200 may control verifying voltages for verifying programming states to have different level change start timings. Since levels of verifying voltages may be sequentially changed, instead of being changed all at once, as a program loop count increases, an efficient operation may be performed.

An embodiment of an operation of the voltage controller 200 for controlling changing of a level of the first verifying voltage VP1 for verifying the first programming state P1 of FIG. 6 will now be explained with reference to FIGS. 10, 11B, and 12A. The voltage controller 200 may compare program loop count information generated by the program loop counter 210 with control information, and may control a level of a first verifying voltage to be changed by using the control information level parameter VVL corresponding to a comparison result. For example, first, when the program loop counter 210 generates program loop count information indicating an L^(th) programming loop, the voltage controller 200 may compare the program loop count information with the program loop number parameter PLN and may control a first verifying voltage to have a level of the 1-1 verifying voltage V_(va1) by using the verifying voltage level parameter VVL corresponding to a comparison result. Next, when the program loop counter 210 generates program loop count information indicating an L+1^(th) programming loop, the voltage controller 200 may compare the program loop count information with the program loop number parameter PLN and may control the first verifying voltage to have a level of a 1-2 verifying voltage V_(va2) by using the verifying voltage level parameter VVL corresponding to a comparison result. In this manner, the voltage controller 200 may control a level of a second verifying voltage for verifying a second programming state of memory cells and a level of a third verifying voltage for verifying a third programming state of the memory cells. However, the inventive concepts are not limited thereto, and any of various other methods of changing a level of a verifying voltage may be used.

An operation of the voltage controller 200 to control changing of a level of the second verifying voltage VP2 for verifying the second programming state P2 of FIG. 6 will now be explained with reference to FIGS. 10, 11A, and 12B. In an embodiment, the voltage controller 200 may control generation of a second verifying voltage whose level gradually decreases as a programming loop is executed on memory cells.

There is a difference from FIG. 12A in that the voltage controller 200 may set a change start verify voltage to the 2-1 verifying voltage V_(vb1) by using the change start verify voltage level parameter SVL and may set a level change degree to a second offset voltage V_(os2) by using the level change degree start loop parameter SL. The second offset voltage V_(os2) may have a level that is higher than that of the first offset voltage V_(os1), and the 2-1 verifying voltage V_(vb1) may have a level that is higher than that the 1-1 verifying voltage V_(va1). As shown in FIG. 12B as an example, the 2-1 verifying voltage V_(vb1) for programming loop M is decreased by the second offset voltage V_(os2) to 2-2 verifying voltage V_(vb2) for programming loop M+1. The 2-2 verifying voltage V_(vb2) for programming loop M+1 is decreased by the second offset voltage V_(os2) to 2-3 verifying voltage V_(vb3) for programming loop M+2. The 2-3 verifying voltage V_(vb3) for programming loop M+2 is decreased by the second offset voltage V_(os2) to 2-4 verifying voltage V_(vb4) for programming loop M+3. The 2-4 verifying voltage V_(vb4) for programming loop M+3 is decreased by the second offset voltage V_(os2) to 2-5 verifying voltage V_(vb5) for programming loop M+4. The 2-5 verifying voltage V_(vb5) for programming loop M+4 is decreased by the second offset voltage V_(os2) to 2-6 verifying voltage V_(vb6) for programming loop M+5.

An operation of the voltage controller 200 to control changing of a level of the third verifying voltage VP3 for verifying the third programming state P3 of FIG. 6 will now be explained with reference to FIGS. 10, 11A, and 12C. In an embodiment, the voltage controller 200 may control generation of a third verifying voltage whose level gradually decreases as a programming loop is executed on memory cells.

There is a difference from FIG. 12A in that the voltage controller 200 may set a change start verify voltage to a 3-1 verifying voltage V_(vc1) by using the change start verify voltage level parameter SVL, and may set a level change degree to a third offset voltage V_(os3) by using the level change degree parameter LCD. Also, the voltage controller 200 may set an N^(th) programming loop to a level change start loop by using the level change start loop parameter SL. The third offset voltage V_(os3) may have a level that is higher than that of the second offset voltage V_(os2) and the 3-1 verifying voltage V_(vc1) may have a level that is higher than that of the 2-1 verifying voltage V_(vb1). As shown in FIG. 12C as an example, the 3-1 verifying voltage V_(vc1) for programming loop N is decreased by the third offset voltage V_(os3) to 3-2 verifying voltage V_(vc2) for programming loop N+1. The 3-2 verifying voltage V_(vc2) for programming loop N+1 is decreased by the third offset voltage V_(os3) to 3-3 verifying voltage V_(vc3) for programming loop N+2. The 3-3 verifying voltage V_(vc3) for programming loop N+2 is decreased by the third offset voltage V_(os3) to 3-4 verifying voltage V_(vc4) for programming loop N+3. The 3-4 verifying voltage V_(vc4) for programming loop N+3 is decreased by the third offset voltage V_(os3) to 3-5 verifying voltage V_(vc5) for programming loop N+4.

As such, the voltage controller 200 may control levels of a first verifying voltage, a second verifying voltage, and a third verifying voltage to be differently changed. Since a change amount of a threshold voltage increases as memory cells have a higher threshold voltage as described with reference to FIGS. 8A and 8B, in order to form a desired threshold voltage distribution, the voltage controller 200 may change voltage levels so that a level change degree of a third verifying voltage is greater than a level change degree of a second verifying voltage (i.e., V_(os3)>V_(os2)), and the level change degree of the second verifying voltage is greater than a level change degree of a first verifying voltage (i.e., V_(os2)>V_(os1)). The voltage controller 200 may control the voltage generator so that a level difference between the 1-1 verifying voltage V_(va1) that is a change start verify voltage of the first verifying voltage and a change start verify voltage V_(vb1) of the second verifying voltage is less than a level difference between the change start verify voltage V_(vb1) of the second verifying voltage and a change start verify voltage V_(vc1) of the third verifying voltage. That is, the voltage controller 200 may control a level difference between adjacent verifying voltages to increase as verifying voltages have higher levels. Also, the voltage controller 200 may control verifying voltages to be changed by differently setting programming loops in which levels of the verifying voltages start to be changed, thereby making it possible to efficiently change a level.

FIGS. 13A, 13B, 13C and 13D illustrate graphs for explaining an operation of the voltage controller 200 to control changing of a level of a verifying voltage according to various embodiments of the inventive concept.

Referring to FIGS. 10 and 13A, the voltage controller 200 may control a level of a first verifying voltage to be changed by a level change degree that varies according to each programming loop, in contrast to the embodiment described with respect to FIG. 12A. The voltage controller 200 may change a level of a first verifying voltage by the first offset voltage V_(os1) that is a constant level change degree in the embodiment described with respect to FIG. 12A, whereas the voltage controller 200 may change a level of a first verifying voltage by any of offset voltages V_(os1-1) through V_(os1-5) that are different from one another for programming loops L+1 through L+5 in the embodiment described with respect to FIG. 13A.

Referring to FIGS. 10 and 13B, the voltage controller 200 may control a level of a first verifying voltage to be changed at every predetermined loop interval, in contrast to the embodiment described with respect to FIG. 12A. That is, the voltage controller 200 may control a level of a verifying voltage to be changed at every predetermined loop interval, instead of being changed at every programming loop. In an embodiment, control information may further include a loop interval parameter, and the voltage controller 200 may control a level of a verifying voltage to be changed by using the loop interval parameter. The loop interval as shown in FIG. 13B is two programming loops. However, the inventive concepts are not limited thereto, and any of various other loop intervals may be set. In another embodiment, the predetermined loop interval may not be fixed, and may vary as a program loop count increases.

Referring to FIGS. 10 and 13C, the voltage controller 200 may control a level of a first verifying voltage to be fixed after a programming loop is executed on memory cells a predetermined number of times, in contrast to the embodiment described with respect to FIG. 12A. For example, the voltage controller 200 may control a level of at least one verifying voltage from among the first verifying voltage VP1, the second verifying voltage VP2, and the third verifying voltage VP3 of FIG. 6 to be fixed after a specific programming loop. That is, the voltage controller 200 may control a first verifying voltage to be a level of a predetermined verifying voltage V_(vak) after a P^(th) programming loop P. However, the inventive concept is not limited thereto, and the voltage controller 200 may control a level of the first verifying voltage to be changed again after a P+3^(th) programming loop (not shown) for example, and various other modifications may be made.

Referring to FIGS. 10 and 13D, the voltage controller 200 may control a first verifying voltage to have a level that is higher than a level of a first reference voltage V_(ref1) corresponding to the first verifying voltage while programming loops L through J+1 are initially performed, and may control the first verifying voltage to have a level that is lower than the level of the first reference voltage V_(ref1) corresponding to the first verifying voltage while the programming loops J+1 through . . . are subsequently performed. In an embodiment, the first reference voltage V_(ref1) may correspond to a conventional verifying voltage for verifying a first programming state. Furthermore, the voltage controller 200 may control a level of any of verifying voltages other than the first verifying voltage to be lower than a level of each corresponding reference voltage, and thus a program loop count needed to complete a programming operation may be reduced, thereby rapidly performing the programming operation. Also, control information stored in the control information storage unit 230 may include a reference voltage parameter corresponding to each verifying voltage, and the voltage controller 200 may control a verifying operation to be performed by using a reference voltage having a constant level without changing a level of a verifying voltage by using the reference voltage parameter. Also, in an embodiment, a change start verify voltage level parameter may be generated by using the reference voltage parameter and a level change degree parameter.

Changing of levels of verifying voltages may be controlled by selecting a control method suitable for a programming operation condition of a memory device from among various control methods of the voltage controller 200 as described with respect to FIGS. 13A through 13D. Also, the various control methods of the voltage controller 200 as described with respect to FIGS. 13A through 13D may be used to control changing of levels of a second verifying voltage and a third verifying voltage, and may also be used to control changing of a level of a verifying voltage of memory cells that may store three or more bits of data and single-level cells SLCs.

FIGS. 14A and 14B each illustrate a block diagram for explaining a control operation of a voltage controller according to embodiments of the inventive concept.

Referring to FIG. 14A, a voltage controller 200′ includes a program loop counter 210′, a verifying voltage level control signal generator 220′, and a control information storage unit 230′. The verifying voltage level control signal generator 220′ includes a subtractor 221′ and an accumulator 222′. The accumulator 222′ receives program loop count information PLCI from the program loop counter 210′. Also, the accumulator 222′ receives level change degree information LCDI from the control information storage unit 230′. The accumulator 222′ may generate accumulation information ACI including an accumulation amount obtained by accumulating a level change degree corresponding to the level change degree information LCDI whenever the program loop count information PLCI is received. The accumulator 222′ may transmit the accumulation information ACI to the subtractor 221′. The subtractor 221′ receives change start verifying voltage level information SVLI from the control information storage unit 230′. The subtractor 221′ generates a voltage control signal CTRL_vol1′ after subtracting the accumulation amount included in the accumulation information ACI from a change start verify voltage level corresponding to the change start verifying voltage level information SVLI. In an embodiment, the level change degree information LCDI may be the level change degree parameter LCD of FIG. 11A, and the change start verifying voltage level information SVLI may be the change start verify voltage level parameter SVL of FIG. 11A.

The voltage controller 200′ may control changing of a level of a verifying voltage as shown in the graph of FIG. 12A or the like in this manner. Also, although not shown in FIG. 14A, in an embodiment, the program loop counter 210′ may receive level change start loop information from the control information storage unit 230′ and may control the accumulator 222′ and the subtractor 221′ to be activated/deactivated based on the level change start loop information. That is, the program loop counter 210′ may compare the program loop count information PLCI with the level change start loop information and may activate the accumulator 222′ and the subtractor 221′ which were deactivated when the program loop count information PLCI and the level change start loop information are the same. In another embodiment, the voltage controller 200′ may include an activation controller, and may control the accumulator 222′ and the subtractor 221′ to be activated/deactivated based on the level change start loop information and the program loop count information PLCI.

Referring to FIG. 14B, a voltage controller 200″ includes a program loop counter 210″, a verifying voltage level control signal generator 220″, and a control information storage unit 230″. The verifying voltage level control signal generator 220″ includes a comparison result-based control signal generator 221″ and an information comparator 222″. The information comparator 222″ may compare program loop count information PLCI generated by the program loop counter 210″ with control information CSI and may generate a comparison result CRI. The information comparator 222″ may transmit the comparison result CRI to the comparison result-based control signal generator 221″. The comparison result-based control signal generator 221″ may generate a voltage control signal CTRL_vol1″ for controlling generation of a verifying voltage having a verifying voltage level corresponding to the comparison result CRI. For example, referring to FIG. 11B, when the program loop counter 210″ generates program loop count information indicating an L^(th) program loop, the information comparator 222″ may compare the program loop count information with the program loop number parameter PLN (i.e., control information CSI) and may generate the voltage control signal CTRL_vol1″ for controlling a first verifying voltage having a level of the 1-1 verifying voltage V_(va1) to be generated by using the verifying voltage level parameter VVL corresponding to a comparison result.

FIG. 15 illustrates a block diagram for explaining an operation of a program loop counter 310 according to an embodiment of the inventive concept.

Referring to FIG. 15 , a voltage controller 300 includes the program loop counter 310, a verifying voltage level control signal generator 320, and a control information storage unit 330. The verifying voltage level control signal generator 320 includes a first verifying voltage level control signal generator 321 that generates a control signal for changing a level of a first verifying voltage for verifying a first programming state, a second verifying voltage level control signal generator 323 that generates a control signal for changing a level of a second verifying voltage for verifying a second programming state, and a third verifying voltage level control signal generator 325 that generates a control signal for changing a level of a third verifying voltage for verifying a third programming state. However, the inventive concept is not limited thereto, and the voltage controller 300 of a memory device including memory cells that may store three or more bits of data or single-level cells SLCs may include more verifying voltage level control signal generators than described with respect to FIG. 15 .

The program loop counter 310 may receive level change start loop information from the control information storage unit 330. The program loop counter 310 may control the first through third verifying voltage level control signal generators 321, 323, and 325 to be activated/deactivated by transmitting an enable/disable signal to each of the first through third verifying voltage level control signal generators 321, 323, and 325, based on the level change start loop information. That is, referring to FIG. 11A, since a level change start loop of a first verifying voltage for verifying the first programming state P1 is the L^(th) program loop L, the program loop counter 310 may activate the first verifying voltage level control signal generator 321 when a program loop count corresponds to the L^(th) program loop L. In this manner, the program loop counter 310 may activate the second and third verifying voltage level control signal generators 323 and 325 when a program loop count respectively corresponds to the M^(th) program loop M and the Nth program loop N. In this manner, the voltage controller 300 may individually control changing of levels of verifying voltages for verifying programming states, thereby leading to efficient control.

FIG. 16 illustrates a block diagram of a voltage controller 400 according to another embodiment of the inventive concept. FIGS. 17A and 17B each illustrate a graph for explaining an operation of the voltage controller 400 to control changing of a level of a verifying voltage according to the embodiment described with respect to FIG. 16 .

Referring to FIGS. 16, 17A, and 17B, the voltage controller 400 includes a program loop counter 410, a verifying voltage level control signal generator 420, a control information storage unit 430, and a temperature information generator 440. As shown in FIG. 17A, the voltage controller 400 may set a level change degree of a predetermined verifying voltage under a first temperature condition to a first offset voltage V_(os1) and may control a level of the predetermined verifying voltage to decrease from change start verify voltage V_(va1) by a level of the first offset voltage V_(os1) in every programming loop L+1 through L+5 to respectively provide verify voltages V_(va2) to V_(va6). In an embodiment as shown in FIG. 17B, the voltage controller 400 may set a level change degree of a predetermined verifying voltage under a second temperature condition to a first offset voltage V_(os1), and may control a level of the predetermined verifying voltage to decrease from change start verify voltage V_(va1′) by a level of the first offset voltage V_(os1), in every programming loop L+1 through L+5 to respectively provide verify voltages V_(va2′) to V_(va6′).

The first temperature condition may have a temperature higher than a temperature of the second temperature condition, and the voltage controller 400 may control a level of a change start verify voltage V_(va1) of the verifying voltage of FIG. 17A and the first offset voltage V_(os1) to be respectively less than a level of a change start verify voltage V_(va1′) of the verifying voltage of FIG. 17B and the first offset voltage V_(os1′). Since a change amount of a threshold voltage of each of a fast cell and a slow cell per time increases as a temperature decreases as described with reference to FIGS. 8A and 8B, the voltage controller 400 may control changing of a verifying voltage by increasing a level of a change start verify voltage and a level change degree as a temperature of a temperature condition decreases.

A detailed method of the voltage controller 400 to control changing of a level of a verifying voltage will now be explained. The temperature information generator 440 may generate temperature information about a temperature inside or outside a memory device including the voltage controller 400. The temperature information may indicate a temperature inside or outside the memory device, and may be a predetermined coefficient that varies according to a temperature. Also, in an embodiment, the temperature information generator 440 may be a temperature sensor, and may be separately provided in the memory device, instead of being included in the voltage controller 400.

A voltage control signal CTRL_vol2 transmitted by the voltage controller 400 to the voltage generator 130 of FIG. 2 may include temperature information received from the temperature information generator 440 and a control signal generated by the verifying voltage level control signal generator 420. The temperature information may include a coefficient according to a temperature. For example, the coefficient according to the temperature may increase as the temperature decreases. The voltage generator 130 of FIG. 2 may generate verifying voltages whose levels are changed based on the voltage control signal CTRL_vol2. In an embodiment, the voltage generator 130 may perform a calculation on the coefficient according to the temperature and the control signal and may generate verifying voltages based on a calculation result.

FIG. 18A illustrates a block diagram for explaining an operation of a voltage controller 500 to control changing of a level of a verifying voltage according to another embodiment of the inventive concept. FIG. 18B is a diagram illustrating control information needed during an operation of the voltage controller 500 according to the embodiment described with respect to FIG. 18A.

Referring to FIG. 18A, the voltage controller 500 includes a program loop counter 510, a verifying voltage level control signal generator 520, a control information storage unit 530, and a temperature information generator 540. The verifying voltage level control signal generator 520 according to an embodiment may receive temperature information from the temperature information generator 540, and may receive control information from the control information storage unit 530. The verifying voltage level control signal generator 520 may generate a voltage control signal CTRL_vol3 based on the temperature information and the control information. Referring to FIG. 18B, control information including a change start verify voltage level parameter SVL and a level change degree parameter LCD that vary according to a temperature condition may be stored in the control information storage unit 530. Accordingly, the voltage controller 500 may change a level of a verifying voltage by referring to the change start verify voltage level parameter SVL and the level change degree parameter LCD corresponding to a temperature condition based on the temperature information. For example, it is assumed that a second temperature condition Temp.2 may have a temperature lower than a temperature of a first temperature condition Temp.1 and the voltage controller 500 changes a level of a first verifying voltage to verify the first programming state P1 of FIG. 6 . The voltage controller 500 may control changing of the level of the first verifying voltage by making a level of a change start verify voltage V_(va1′) under the second temperature condition Temp.2 greater than a level of a change start verify voltage V_(va1) under the first temperature condition Temp.1 and making a level change degree V_(os1′), under the second temperature condition Temp.2 greater than a level change degree V_(os1) under the first temperature condition Temp.1. The voltage controller 500 may similarly change start verify voltage V_(vb1) to change start verify voltage V_(vb1′), change start verify voltage V_(vc1) to change start verify voltage V_(vc1′), level change degree V_(os2) to level change degree V_(os2′) and level change degree V_(os3) to level change degree V_(os3′) under the second temperature condition Temp. 2.

However, the inventive concept is not limited thereto, and control information may include the verifying voltage level parameter VVL that varies according to a temperature condition as shown in FIG. 11B, and the voltage controller 500 may control changing of a level of a verifying voltage based on the control information and temperature information.

FIG. 19A illustrates a block diagram for explaining an operation of a voltage controller 600 to control changing of a level of a verifying voltage according to another embodiment of the inventive concept. FIG. 19B illustrates a graph for explaining a method of a temperature information generator 640 to generate temperature information according to the embodiment described with respect to FIG. 19A. In FIG. 19B, the vertical axis represents the temperature coefficient, and the horizontal axis represents temperature.

Referring to FIG. 19A, the voltage controller 600 includes a program loop counter 610, a verifying voltage level control signal generator 620, a control information storage unit 630, a temperature information generator 640, and a control signal integrator 650. Referring to FIG. 19B, by using a detected temperature inside or outside a memory device, the temperature information generator 640 may generate a coefficient according to the detected temperature. In an embodiment, the temperature information generator 640 may generate a first coefficient TC_(hot) at a first temperature Thot that is high, and may generate a second coefficient TC_(cold) at a second temperature Tcold that is low. The second coefficient TC_(cold) may be greater than the first coefficient TC_(hot). That is, the temperature information generator 640 may generate a coefficient that increases as a detected temperature decreases.

The control signal integrator 650 according to an embodiment may receive a voltage control signal from the verifying voltage level control signal generator 620, and may receive temperature information including the generated coefficient from the temperature information generator 640. The control signal integrator 650 may perform a predetermined calculation on the generated coefficient and the voltage control signal, to generate a voltage control integrated signal CTRL_vol3. For example, the control signal integrator 650 may generate the voltage control integrated signal CTRL_vol3 by multiplying the generated coefficient by the voltage control signal. The voltage controller 600 may control a level of a verifying voltage to be changed by varying at least one of a change start verify voltage level and a level change degree according to a temperature condition by using a generated coefficient, even without a parameter that varies according to a temperature condition included in control information of FIGS. 11A and 11B.

FIGS. 20A and 20B are graphs for explaining an overall operation of the voltage controller 121 shown in FIG. 2 according to an embodiment of the inventive concept.

Referring to FIGS. 2 and 20A, the voltage controller 121 may control changing of a level of each of verifying voltages based on at least one of a programming state of memory cells to be verified and temperature information about a temperature inside or outside the memory device 100. In an embodiment, the voltage controller 121 may control changing of a level of each verifying voltage according to a programming state of memory cells to be verified. That is, the voltage controller 121 may control changing of a level of each verifying voltage by increasing a change start verify voltage level and a level change degree of the verifying voltage as a level of the verifying voltage corresponding to a programming state to be verified increases. For example, as shown in FIG. 20A the voltage controller 121 may control changing of a level of each verifying voltage by making a change start verify voltage level and a level change degree V_(os2) of a second verifying voltage for verifying a second programming state P2 greater than a change start verify voltage level and a level change degree V_(os1) of a first verifying voltage for verifying a first programming state P1. Also, the voltage controller 121 may control changing of a level of each verifying voltage by making a change start verify voltage level and a level change degree V_(os3) of a third verifying voltage for verifying a third programming state P3 greater than the change start verify voltage level and the level change degree V_(os2) of the second verifying voltage for verifying the second programming state P2. In another embodiment, the voltage controller 112 may control verifying voltages to have different level change start timings by differently setting level change start loops of the first verifying voltage through the third verifying voltage.

Moreover, as shown in FIG. 20B, the voltage controller 121 may control changing of a level of each verifying voltage according to temperature information about a temperature inside or outside the memory device 100 and a programming state of memory cells to be verified. For example, the voltage controller 121 may control changing of a level of a third verifying voltage by making a level of a change start verify voltage V_(vc1′) and a level change degree V_(os3′) of a third verifying voltage for verifying a third programming state P3 under a second temperature condition T2 condition greater than a level of a change start verify voltage V_(vc1) and a level change degree V_(os3) of a third verifying voltage for verifying the third programming state P3 under a first temperature condition T1 condition. Similarly, the voltage generator 121 may make a level of a change start verify voltage V_(vb1′) and a level change degree V_(os2′) of a second verifying voltage for verifying a second programming state P2 under a second temperature condition T2 condition greater than a level of a change start verify voltage V_(vb1) and a level change degree V_(os2) of a second verifying voltage for verifying the second programming state P2 under a first temperature condition T1 condition. Likewise, for verifying the first programming state P1, the voltage generator 121 may make a level of a change start verify voltage V_(va1′) and a level change degree V_(os1′) under a second temperature condition T2 condition greater than a level of a change start verify voltage V_(va1) and a level change degree V_(os1) under a first temperature condition T1 condition.

The voltage controller 121 according to an embodiment may control changing of a level of each verifying voltage based on at least one of a programming state to be verified and temperature information about a temperature inside or outside the memory device 100, in order to perform a verifying operation considering that a threshold voltage of a memory cell is shifted.

FIG. 21 illustrates a flowchart for explaining a programming operation in a memory device such as memory device 100 shown in FIG. 2 for example, according to an embodiment of the inventive concept. In the description that follows, it is assumed that memory device 100 includes voltage controller 200 shown in FIG. 10 for example. However, in other embodiments memory device 100 may include any of the voltage controllers of the various embodiments previously described.

Referring to FIG. 21 , FIG. 2 and FIG. 10 for example, in operation S100 a program loop counter such as program loop counter 210 initializes a program loop count before a programming operation starts. In operation S110, a level of a programming voltage to be applied to memory cells of the memory cell array 110 connected to a selected word line is determined. The level of the programming voltage may be determined by control logic 120 to correspond to a pulse voltage that increases by a predetermined step voltage by using the program loop count. In operation S120, the determined programming voltage as provided by voltage generator 130 is applied to the selected word line via row decoder 140 for example. Next, in order to verify the memory cells connected to the selected word line, a level of a verifying voltage is determined by voltage controller 200 for example. In an embodiment, in operation S130 the level of the verifying voltage may be changed based on at least one of a programming state to be verified and temperature information. In operation S140, a verifying operation is performed by applying the verifying voltage whose level has been changed as provided by voltage generator 130 to the selected word line via row decoder 140. In operation S150, it is determined by control logic 120 for example whether all of the memory cells of the selected word line pass the verifying operation. When it is determined in operation S150 that all of the memory cells pass the verifying operation, processing proceeds to operation S160 where it is determined that the programming operation is completed. When it is determined in operation S150 that all of the memory cells do not pass the verifying operation, processing proceeds to operation S170 where it is determined by control logic 120 whether the counted program loop count exceeds a maximum value. When it is determined in operation S170 that the counted program loop count exceeds the maximum value, processing proceeds to operation S180 where it is determined that the programming operation fails. When it is determined in operation S170 that the counted program loop count does not exceed the maximum value, processing proceeds to operation S190 where the program loop count is increased, and a next programming loop is executed thereafter beginning at operation S110.

FIG. 22 illustrates a block diagram of an example where a memory device is applied to a memory card system 1000 according to embodiments of the inventive concept.

Referring to FIG. 22 , the memory card system 1000 includes a host 1100 and a memory card 1200. The host 1100 includes a host controller 1110 and a host connector 1120. The memory card 1200 includes a card connector 1210, a card controller 1220, and a memory device 1230. In this case, the memory card 1200 may be realized by using the embodiment of FIG. 1 , or any of the other variously disclosed embodiments.

The host 1100 may write data to the memory card 1200 or may read data stored in the memory card 1200. The host controller 1110 may transmit a command CMD, a clock signal CLK generated by a clock generator (not shown) in the host 1100, and data DATA to the memory card 1200 through the host connector 1120.

The card controller 1220 may synchronize data with a clock signal generated by a clock signal (not shown) in the card controller 1220 and may store the data in the memory device 1230, in response to a command received through the card connector 1210. The memory device 1230 may store the data transmitted from the host 1100.

The memory card 1200 may be for example any of a compact flash card (CFC), a microdrive, a smart media card (SMC), a multimedia card (MMC), a security digital card (SDC), a memory stick, and a USB flash memory driver or the like.

FIG. 23 illustrates a block diagram of a computing system 2000 including a memory device according to embodiments of the inventive concept.

Referring to FIG. 23 , the computing system 2000 includes a memory system 2100, a processor 2200, a RAM 2300, an input/output device 2400, and a power supply 2500. The computing system 2000 may communicate with a video card, a sound card, a memory card, or a USB device or the like for example, or may further include ports for communicating with other electronic devices. The computing system 2000 may be for example a personal computer, or may be a portable electronic device such as a notebook computer, a mobile phone, a personal digital assistant (PDA), or a camera, or the like.

The processor 2200 may perform specific calculations or tasks. According to an embodiment, the processor 2200 may be a microprocessor or a central processing unit (CPU). The processor 2200 may communicate with the RAM 2300, the input/output device 2400, and the memory system 2100 through a bus 2600 such as an address bus, a control bus, or a data bus. According to an embodiment, the processor 2200 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

In this case, the memory system 2100 may be realized by using the embodiment of FIG. 1 , or any of the other variously disclosed embodiments. In detail, a memory device 2110 may perform a verifying operation by changing a level of a verifying voltage based on at least one of a programming state of memory cells to be verified and temperature condition about a temperature inside or outside the memory device 2110.

The RAM 2300 may store data needed during an operation of the computing system 2000. For example, the RAM 2300 may be for example a dynamic random-access memory (DRAM), a mobile DRAM, a static RAM (SRAM), a phase-change RAM (PRAM), a ferroelectric RAM (FRAM), a resistive RAM (RRAM), and/or a magnetoresistive RAM (MRAM). The input/output device 2400 may include an input device such as for example a keyboard, a keypad, or a mouse, or the like, and an output device such as a printer or a display. The power supply 2500 may supply an operating voltage needed during an operation of the computing system 2000.

FIG. 24 illustrates a block diagram of an example where a memory device is applied to a solid-state disk (SSD) system 3000 according to embodiments of the inventive concept.

Referring to FIG. 24 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 transmits/receives a signal SGL to/from the host 3100 through a signal connector, and receives power PWR through a power connector. The SSD 3200 includes a SSD controller 3210, an auxiliary power supply 3220, and a plurality of memory devices 3230, 3240, and 3250 connected to SSD controller 3210 via channels Ch1, Ch2, . . . Chn. In this case, the SSD 3200 may be realized by using the embodiment of FIG. 1 , or any of the other variously disclosed embodiments. In detail, the SSD 3200 may perform a verifying operation by changing a level of a verifying voltage based on at least one of a programming state of memory cells to be verified and temperature information about a temperature inside or outside the SSD 3200.

FIG. 25 illustrates a block diagram of an example where a memory device is applied to a universal flash storage (UFS) system 4000 according to embodiments of the inventive concept.

Referring to FIG. 25 , the UFS system 4000 includes a UFS host 4100, UFS device1 4200, UFS device2 4300, an embedded UFS device 4400, and a removable UFS card 4500. The UFS host 4100 may for example be an application processor of a mobile device. Each of the UFS host 4100, the UFS devices 4200 and 4300, the embedded UFS device 4400, and the removable UFS card 4500 may communicate with external devices through a UFS protocol. At least one of the UFS devices 4200 and 4300, the embedded UFS device 4400, and the removable UFS card 4500 may include the memory device 100 of FIG. 1 .

The embedded UFS device 4400 and the removable UFS card 4500 may communicate with each other through a protocol other than the UFS protocol. The UFS host 4100 and the removable UFS card 4500 may communicate through various card protocols such as for example USB flash drive (UFD), MMC, secure digital (SD), miniSD, and microSD.

A memory card, a nonvolatile memory device, and a card controller according to the inventive concept may be mounted by using any of various packages. For example, a flash memory device and/or a memory controller according to the inventive concept may be mounted by using any of packages such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flatpack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP).

FIG. 26 is a diagram illustrating a memory device 5400 according to another example embodiment.

Referring to FIG. 26 , a memory device 5400 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, separate from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, the bonding metals may include copper (Cu) using a Cu-to-Cu bonding. The example embodiment, however, may not be limited thereto. For example, the bonding metals may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit region PERI and the cell region CELL of the memory device 5400 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate 5210, an interlayer insulating layer 5215, a plurality of circuit elements 5220 a, 5220 b, and 5220 c formed on the first substrate 5210, first metal layers 5230 a, 5230 b, and 5230 c respectively connected to the plurality of circuit elements 5220 a, 5220 b, and 5220 c, and second metal layers 5240 a, 5240 b, and 5240 c formed on the first metal layers 5230 a, 5230 b, and 5230 c. In an example embodiment, the first metal layers 5230 a, 5230 b, and 5230 c may be formed of tungsten having relatively high electrical resistance, and the second metal layers 5240 a, 5240 b, and 5240 c may be formed of copper having relatively low electrical resistance.

In an example embodiment illustrate in FIG. 26 , although only the first metal layers 5230 a, 5230 b, and 5230 c and the second metal layers 5240 a, 5240 b, and 5240 care shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 5240 a, 5240 b, and 5240 c. At least a portion of the one or more additional metal layers formed on the second metal layers 5240 a, 5240 b, and 5240 c may be formed of aluminum or the like having a lower electrical resistance than those of copper forming the second metal layers 5240 a, 5240 b, and 5240 c.

The interlayer insulating layer 5215 may be disposed on the first substrate 5210 and cover the plurality of circuit elements 5220 a, 5220 b, and 5220 c, the first metal layers 5230 a, 5230 b, and 5230 c, and the second metal layers 5240 a, 5240 b, and 5240 c. The interlayer insulating layer 5215 may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 5271 b and 5272 b may be formed on the second metal layer 5240 b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 5271 b and 5272 b in the peripheral circuit region PERI may be electrically bonded to the upper bonding metals 5371 b and 5372 b of the cell region CELL. The lower bonding metals 5271 b and 5272 b and the upper bonding metals 5371 b and 5372 b may be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals 5371 b and 5372 b in the cell region CELL may be referred as first metal pads and the lower bonding metals 5271 b and 5272 b in the peripheral circuit region PERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate 5310 and a common source line 5320. On the second substrate 5310, a plurality of word lines 5331 to 5338 (i.e., 5330) may be stacked in a direction (a Z-axis direction), perpendicular to an upper surface of the second substrate 5310. At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines 5330, respectively, and the plurality of word lines 5330 may be disposed between the at least one string select line and the at least one ground select line.

In the bit line bonding area BLBA, a channel structure CH may extend in a direction (a Z-axis direction), perpendicular to the upper surface of the second substrate 5310, and pass through the plurality of word lines 5330, the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer 5350 c and a second metal layer 5360 c. For example, the first metal layer 5350 c may be a bit line contact, and the second metal layer 5360 c may be a bit line. In an example embodiment, the bit line 5360 c may extend in a first direction (a Y-axis direction), parallel to the upper surface of the second substrate 5310.

In an example embodiment illustrated in FIG. 26 , an area in which the channel structure CH, the bit line 5360 c, and the like are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line 5360 c may be electrically connected to the circuit elements 5220 c providing a page buffer 5393 in the peripheral circuit region PERI. The bit line 5360 c may be connected to upper bonding metals 5371 c and 5372 c in the cell region CELL, and the upper bonding metals 5371 c and 5372 c may be connected to lower bonding metals 5271 c and 5272 c connected to the circuit elements 5220 c of the page buffer 5393.

In the word line bonding area WLBA, the plurality of word lines 5330 may extend in a second direction (an X-axis direction), parallel to the upper surface of the second substrate 5310 and perpendicular to the first direction, and may be connected to a plurality of cell contact plugs 5341 to 5347 (i.e., 5340). The plurality of word lines 5330 and the plurality of cell contact plugs 5340 may be connected to each other in pads provided by at least a portion of the plurality of word lines 5330 extending in different lengths in the second direction. A first metal layer 5350 b and a second metal layer 5360 b may be connected to an upper portion of the plurality of cell contact plugs 5340 connected to the plurality of word lines 5330, sequentially. The plurality of cell contact plugs 5340 may be connected to the peripheral circuit region PERI by the upper bonding metals 5371 b and 5372 b of the cell region CELL and the lower bonding metals 5271 b and 5272 b of the peripheral circuit region PERI in the word line bonding area WLBA.

The plurality of cell contact plugs 5340 may be electrically connected to the circuit elements 5220 b forming a row decoder 5394 in the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elements 5220 b of the row decoder 5394 may be different than operating voltages of the circuit elements 5220 c forming the page buffer 5393. For example, operating voltages of the circuit elements 5220 c forming the page buffer 5393 may be greater than operating voltages of the circuit elements 5220 b forming the row decoder 5394.

A common source line contact plug 5380 may be disposed in the external pad bonding area PA. The common source line contact plug 5380 may be formed of a conductive material such as a metal, a metal compound, poly silicon, or the like, and may be electrically connected to the common source line 5320. A first metal layer 5350 a and a second metal layer 5360 a may be stacked on an upper portion of the common source line contact plug 5380, sequentially. For example, an area in which the common source line contact plug 5380, the first metal layer 5350 a, and the second metal layer 5360 a are disposed may be defined as the external pad bonding area PA.

Input-output pads 5205 and 5305 may be disposed in the external pad bonding area PA. Referring to FIG. 26 , a lower insulating film 5201 covering a lower surface of the first substrate 5210 may be formed below the first substrate 5210, and a first input-output pad 5205 may be formed on the lower insulating film 5201. The first input-output pad 5205 may be connected to at least one of the plurality of circuit elements 5220 a, 5220 b, and 5220 c disposed in the peripheral circuit region PERI through a first input-output contact plug 5203, and may be separated from the first substrate 5210 by the lower insulating film 5201. In addition, a side insulating film may be disposed between the first input-output contact plug 5203 and the first substrate 5210 to electrically separate the first input-output contact plug 5203 and the first substrate 5210.

Referring to FIG. 26 , an upper insulating film 5301 covering the upper surface of the second substrate 5310 may be formed on the second substrate 5310, and a second input-output pad 5305 may be disposed on the upper insulating layer 5301. The second input-output pad 5305 may be connected to at least one of the plurality of circuit elements 5220 a, 5220 b, and 5220 c disposed in the peripheral circuit region PERI through a second input-output contact plug 5303. In the example embodiment, the second input-output pad 5305 is electrically connected to a circuit element 5220 a.

According to embodiments, the second substrate 5310 and the common source line 5320 may not be disposed in an area in which the second input-output contact plug 5303 is disposed. Also, the second input-output pad 5305 may not overlap the word lines 5330 in the direction (the Z-axis direction). Referring to FIG. 26 , the second input-output contact plug 5303 may be separated from the second substrate 5310 in a direction, parallel to the upper surface of the second substrate 5310, and may pass through the interlayer insulating layer 5315 of the cell region CELL to be connected to the second input-output pad 5305.

According to embodiments, the first input-output pad 5205 and the second input-output pad 5305 may be selectively formed. For example, the memory device 5400 may include only the first input-output pad 5205 disposed on the first substrate 5210 or the second input-output pad 5305 disposed on the second substrate 5310. Alternatively, the memory device 5400 may include both the first input-output pad 5205 and the second input-output pad 5305.

A metal pattern provided on an upper most metal layer may be provided as a dummy pattern or the upper most metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI. In addition, in some embodiments, the metal pattern may be provided as an upper metal patterns 5372 a and 5392, a lower metal patterns 5273 a and 5252, and the like.

In the external pad bonding area PA, the memory device 5400 may include the lower metal pattern 5273 a, corresponding to the upper metal pattern 5372 a formed in the upper most metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern 5372 a of the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 5273 a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern 5372 a, corresponding to the lower metal pattern 5273 a formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern 5273 a of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL.

The lower bonding metals 5271 b and 5272 b may be formed on the second metal layer 5240 b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 5271 b and 5272 b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 5371 b and 5372 b of the cell region CELL by a Cu-to-Cu bonding.

Further, in the bit line bonding area BLBA, the upper metal pattern 5392, corresponding to the lower metal pattern 5252 formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern 5252 of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern 5392 formed in the uppermost metal layer of the cell region CELL.

In an example embodiment, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other one of the cell region CELL and the peripheral circuit region PERI. A contact may not be formed on the reinforcement metal pattern.

According to an example embodiment of the inventive concept, a control logic configured to control a plurality of programming loops for programming a plurality of memory cells formed in a cell region CELL to a programming state to be executed and gradually decrease a voltage level of a verifying voltage applied for each program loop to verify the target programming state as a program loop count increases may be formed in a peripheral circuit region PERI (or a lower chip). Furthermore, various circuits essential for a memory operation such as a voltage generator for generating a verifying voltage, a page buffer, and a data input/output circuit may be formed in the peripheral circuit region PERI.

FIG. 27 is a circuit diagram illustrating first and second mats MAT1 and MAT2 included in the cell region CELL of FIG. 26 . A plurality of memory blocks may be included in the first and second mats MAT1 and MAT2. A plurality of cell strings may be included in each of the plurality of memory blocks. For example, a plurality of cell strings, for example, first through fourth cell strings CS11, CS12, CS21, and CS22, are included in one of the memory blocks included in the first mat MAT1, and first through fourth cell strings CS31, CS32, CS41, and CS42, are included in one of the memory blocks included in the second mat MAT2. A plurality of cell strings included in one mat may be formed on a plurality of planes. Each of the first and second mats MAT1 and MAT2 may include a plurality of memory blocks. One of the plurality of memory blocks may include a plurality of string selection lines, for example, first and second string selection lines SSL1 a and SSL1 b, for selecting at least one of the first through fourth cell strings CS11, CS12, CS21, and CS22. For example, when a selection voltage is applied to the first string selection line SSL1 a, the first and second cell strings CS11 and CS12 may be selected. Likewise, when a selection voltage is applied to the second string selection line SSL1 b, the third and fourth cell strings CS21 and CS22 may be selected.

In an example embodiment, the first and second mats MAT1 and MAT2 may have substantially the same physical structure. For example, like the first mat MAT1, the second mat MAT2 may include a plurality of memory blocks and a plurality of cell strings formed on a plurality of planes. Likewise, a plurality of string selection lines SSL2 a and SSL2 b for selecting at least one of a plurality of cell strings may be provided.

Each of the first and second mats MAT1 and MAT2 may be connected to a word line, a ground selection line and a common source line. For example, the cell strings included in the first mat MAT1 may be connected to word lines WL11, WL12, WL13, WL14, WL15, and WL16, a ground selection line GSL1, and a common source line CSL1. The cell strings included in the second mat MAT2 may be connected to word lines WL21, WL22, WL23, WL24, WL25, and WL26, the ground selection line GSL2, and the common source line GSL2. Also, the first and second mats MAT1 and MAT2 do not share a bit line. For example, first bit lines BL1 a and BL1 b may be exclusively connected only to the first mat MAT1. And, second bit lines BL2 a and BL2 b may be exclusively connected only to the second mat MAT2.

In the example embodiment, it is assumed that each mat is connected to two bit lines and six word lines. However, this is merely an example, and each mat may be connected to three or more bit lines or seven or more word lines. Each cell string may include at least one string selection transistor, memory cells, and at least one ground selection transistor. For example, in one cell string CS31, one ground selection transistor GST, a plurality of memory cells MC1 through MC6, and one string selection transistor SST may be sequentially formed in a direction perpendicular to a substrate. Other cell strings CS32, CS41 and CS42 may have the same configuration as the cell string CS31.

In an example embodiment, a string selection line connected to each of the first and second mats MAT1 and MAT2 may be exclusively connected only to a corresponding mat. For example, each of the first and second string selection lines SSL1 a and SSL1 b is connected only to the first mat MAT1. Likewise, each of the string selection lines SSL2 a and SSL2 b may be connected only to the second mat MAT2. Accordingly, a string selection line may select only cell strings included in one mat. Also, cell strings may be independently selected for each mat, by independently controlling each string selection line. For example, the first and second cell strings CS11 and CS12 may be independently selected, by independently applying a selection voltage to the first string selection line SSL1 a. When a selection voltage is applied to the first string selection line SSL1 a, the selection voltage may turn on string selection transistors of the first and second cell strings CS11 and CS12. When the string selection transistors are turned on, memory cells of the first and second cell strings CS11 and CS12 and a bit line may be electrically connected. In contrast, when a non-selection voltage is applied to the first string selection line SSL1 a, the string selection transistors of the first and second cell strings CS11 and CS12 may be turned off, and the first and second cell strings CS11 and CS12 may be non-selected. The memory cells of the first and second cell strings CS11 and CS12 may be electrically separated from the first bit line BL1 a or BL1 b.

The control logic according to an example embodiment of the inventive concept may operate in one of a single mat mode for controlling one of the first and second mats MAT1 and MAT2 and a multi-mat mode for simultaneously controlling the first and second mats MAT1 and MAT2. The control logic may control at least one of a verifying voltage, a voltage level, and a voltage width (or a pulse width) according to an example embodiments of the inventive concept, depending on operating in the single mat mode and operating in the multi-mat mode. For example, the control logic may control a verifying voltage in the single mat mode to have a lower voltage level or a narrower voltage width than that of a verifying voltage in the multi-mat mode. The single mat mode may be referred to as a single plane mode or a 1×-speed mode, and the multi-mat mode may be referred to as a multi-plane mode or a multi-×-speed mode.

Although two mats, (e.g., the first and second mats MAT1 and MAT2), are included in the cell region CELL in FIG. 27 , the inventive concept is not limited thereto. For example, the cell region CELL may include three or more mats, and the control logic may control a verifying voltage according to the inventive concept for the additional mats.

FIG. 28 is a block diagram of a memory device 7000 according to an example embodiment of the inventive concept. A temperature sensor may correspond to the temperature information generator 440 of FIG. 16 .

Referring to FIG. 28 , the memory device 7000 may include an upper chip 7100 and a lower chip 7200. The upper chip 7100 and the lower chip 7200 may be implemented to have a configuration and a connection relationship as described with reference to FIG. 26 . In an example embodiment, the upper chip 7100 may include first and second mats 7110 and 7120, and the lower chip 7200 may include first and second temperature sensors 7210 and 7220. The first temperature sensor 7210 may be aligned with the first mat MAT1 to measure a first temperature of the first mat MAT1. The second temperature sensor 7220 may be aligned with the second mat MAT2 to measure a second temperature of the second mat MAT2.

A control logic according to an example embodiment of the inventive concept may, during a programming operation for the first mat MAT1, control a voltage level of a verifying voltage applied to the first mat MAT1 to verify a target programming state based on the first temperature measured by the first temperature sensor 7210 to decrease in a first pattern as a program loop count increases. Also, the control logic may, during a programming operation for the second mat MAT2, control a voltage level of a verifying voltage applied to the second mat MAT2 to verify a target programming state based on the second temperature measured by the second temperature sensor 7220 to decrease in a second pattern as a program loop count increases.

The term “pattern” may refer to a change in a verifying voltage according to an increase in a program loop count, due to various settings of a change start voltage level parameter, a level change degree parameter, and a level change start loop parameter described with reference to FIG. 11A, etc.

FIG. 29 is a view for describing the cell region CELL of FIG. 26 .

Referring to FIG. 29 , a memory device 8000 may include an upper chip 8100 and a lower chip 8200. The cell region CELL of FIG. 26 may correspond to the upper chip 8100. The channel structure CH of FIG. 26 may include pillars PL of FIG. 29 . The pillars PL may be formed in a direction perpendicular to the lower chip 8200, and may include first portions PL1 adjacent to the lower chip 8200 and second portions PL2 stacked on the first portions PL1.

First conductive materials CM1 and second conductive materials CM2 may be separated by a selection line cut SC provided between the second portions PL2 of the pillars PL. In the example embodiment, at both sides of the pillars PL, first through fifteen conductive materials CM1 through CM15 may be separated from other conductive materials by a word line cut WC.

In an example embodiment, the first portion PL1 may have a cross-sectional area gradually decreasing away from the lower chip 8200, and the second portion PL2 may have a cross-sectional area gradually decreasing away from the first portion PL1. Also, at a boundary between the first portion PL1 and the second portion PL2, a cross-sectional area of the second portion PL2 may be greater than a cross-sectional area of the first portion PL1 as shown in FIG. 29 .

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims. Accordingly, the technical scope of the inventive concept should be defined by the accompanying claims. 

What is claimed is:
 1. A memory device comprising: a lower chip; and an upper chip vertically stacked on the lower chip and bonded to the lower chip, wherein the upper chip comprises a metal layer located adjacent to the lower chip and configured to form a bit line, a substrate vertically spaced apart from the metal layer and configured to form a common source line on a bottom surface of the substrate, and a memory cell array located between the metal layer and the substrate and comprising a plurality of memory cells, and wherein the lower chip comprises a control logic circuit configured to control a plurality of programming loops for programming the plurality of memory cells to a target programming state to be executed, and control a voltage level of a verifying voltage applied for each programming loop to verify the target programming state to gradually decrease as a program loop count increases, wherein the plurality of memory cells comprise a plurality of mats, and wherein the control logic circuit is configured to operate in one of a single mat mode for controlling one of the plurality of mats and a multi-mat mode for simultaneously controlling at least two of the plurality of mats, and is further configured to control the verifying voltage in the single mat mode to be different from the verifying voltage in the multi-mat mode in at least one of the voltage level and a voltage width.
 2. The memory device of claim 1, wherein the control logic circuit is further configured to control the verifying voltage in the single mat mode to have a lower voltage level or a narrower voltage width than that of the verifying voltage in the multi-mat mode.
 3. The memory device of claim 1, wherein the lower chip further comprises a plurality of temperature sensors configured to respectively measure temperatures of the plurality of mats, and wherein the control logic circuit is further configured to control the plurality of mats based on the temperatures of the plurality of mats.
 4. The memory device of claim 1, wherein the memory cell array comprises a pillar comprising: a first portion; and a second portion stacked on the first portion, the first and second portions being formed on the lower chip, wherein the first portion is formed over the lower chip and has a cross-sectional area decreasing away from the lower chip, wherein the second portion is formed on the first portion and has a cross-sectional area decreasing away from the first portion, and wherein, at a boundary between the first portion and the second portion, a cross-sectional area of the second portion is greater than a cross-sectional area of the first portion.
 5. The memory device of claim 1, wherein a degree of first level change of the verifying voltage as the plurality of programming loops are executed when the target programming state is a first programming state is different from a degree of second level change of the verifying voltage as the plurality of programming loops are executed when the target programming state is a second programming state.
 6. The memory device of claim 5, wherein, when a first threshold voltage corresponding the first programming state is higher than a second threshold voltage corresponding to the second programming state, the degree of the first level change is greater than the degree of the second level change.
 7. The memory device of claim 1, wherein a first level change start timing indicating a programming loop in which a level of the verifying voltage starts to be changed when the target programming state is a first programming state is different from a second level change start timing indicating a programming loop in which a level of the verifying voltage starts to be changed when the target programming state is a second programming state.
 8. The memory device of claim 1, wherein the lower chip further comprises a temperature sensor configured to measure a temperature inside or outside the memory device, and wherein the control logic circuit is further configured to control the voltage level of the verifying voltage to be changed based on the temperature inside the memory device.
 9. The memory device of claim 1, wherein the lower chip further comprises a plurality of temperature sensors configured to respectively measure temperatures of the plurality of mats, and wherein a start voltage level of the verifying voltages varies according to the measured temperatures.
 10. The memory device of claim 9, wherein the start voltage level at a first temperature is higher than the start voltage level at a second temperature that is higher than the first temperature.
 11. The memory device of claim 9, wherein a degree of first level change of the verifying voltage as the plurality of programming loops are executed at a first temperature is greater than a degree of second level change of the verifying voltage as the plurality of programming loops are executed at a second temperature that is higher than the first temperature.
 12. The memory device of claim 9, wherein the control logic circuit is further configured to control, when the voltage level of the verifying voltage is lower than a reference voltage level, the voltage level of the verifying voltage applied for each remaining programming loop to be fixed.
 13. A memory device of claim comprising: a lower chip; and an upper chip vertically stacked on the lower chip and bonded to the lower chip, wherein the upper chip comprises a metal layer located adjacent to the lower chip and configured to form a bit line, a substrate vertically spaced apart from the metal layer and configured to form a common source line on a bottom surface of the substrate, and a memory cell array located between the metal layer and the substrate and comprising a plurality of memory cells, and wherein the lower chip comprises a control logic circuit configured to control a plurality of programming loops for programming the plurality of memory cells to a target programming state to be executed, and control a voltage level of a verifying voltage applied for each programming loop to verify the target programming state to gradually decrease as a program loop count increases, wherein the plurality of memory cells comprise a first mat and a second mat, wherein the lower chip further comprises a first temperature sensor aligned with the first mat to measure a first temperature of the first mat, and a second temperature sensor aligned with the second mat to measure a second temperature of the second mat, and wherein the control logic circuit is further configured to control a voltage level of the verifying voltage to decrease in a first pattern based on the first temperature measured during a programming operation for the first mat, and control a voltage level of the verifying voltage to decrease in a second pattern based on the second temperature measured during a programming operation for the second mat.
 14. The memory device of claim 13, wherein a level change degree of the verifying voltage is different for each programming loop of the plurality of programming loops.
 15. The memory device of claim 13, wherein at least one of a level change degree of the verifying voltage and a level change start timing of the verifying voltage is varied based on a type of the target programming state.
 16. A memory device comprising: a lower chip; and an upper chip vertically stacked on the lower chip and bonded to the lower chip, wherein the upper chip comprises a metal layer located adjacent to the lower chip and configured to form a bit line, a substrate vertically spaced apart from the metal layer and configured to form a common source line on a bottom surface of the substrate, and a memory cell array located between the metal layer and the substrate and comprising a plurality of memory cells, and wherein the lower chip comprises a control logic circuit configured to control a plurality of programming loops for programming the plurality of memory cells to a target programming state to be executed, and control a voltage level of a verifying voltage applied for each programming loop to verify the target programming state to gradually decrease as a program loop count increases, and wherein a first level change pattern of the verifying voltage as the plurality of programming loops are executed when the target programming state is a first programming state is different from a second level change pattern of the verifying voltage as the plurality of programming loops are executed when the target programming state is a second programming state.
 17. The memory device of claim 16, wherein the lower chip further comprises a temperature sensor configured to measure a temperature inside or outside of the memory device, and wherein the control logic circuit is configured to control a start voltage level of the verifying voltage to vary according to the measured temperature.
 18. The memory device of claim 17, wherein the start voltage level at a first temperature is higher than the start voltage level at a second temperature that is higher than the first temperature.
 19. The memory device of claim 17, wherein a degree of change of the first level change pattern as the plurality of programming loops are executed at a first temperature is greater than a degree of change of the second level change pattern as the plurality of programming loops are executed at a second temperature that is higher than the first temperature. 